下面是一个D触发器的模块。阅读后指出,哪一种说法不正确? module mydff (clk, reset, load, d, q); input clk, d, reset, load; output q; reg q; always @ (posedge clk or posedge reset or posedge load) begin if (reset==1) // q<=0; else if (load==1) // q<=1; else q<=d; end endmoduleA.该触发器具有异步端口reset和load;B.可以异步置0,可以异步置1C.该触发器是下降沿触发D.该触发器是上升沿触发
下面是一个D触发器的模块。阅读后指出,哪一种说法不正确? module mydff (clk, reset, load, d, q); input clk, d, reset, load; output q; reg q; always @ (posedge clk or posedge reset or posedge load) begin if (reset==1) // q<=0; else if (load==1) // q<=1; else q<=d; end endmodule
A.该触发器具有异步端口reset和load;
B.可以异步置0,可以异步置1
C.该触发器是下降沿触发
D.该触发器是上升沿触发
参考答案和解析
B
相关考题:
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